Gordon Moore's 1965 article is remembered for its forecast of component counts, but it also observed that large systems might in the end be built more economically from smaller functions that are separately packaged and interconnected (Moore, 1965). Sixty years on, that remark describes a main line of development. Server processors are assembled from several dies on one substrate (Naffziger et al., 2021), silicon bridges embedded in organic packages connect dies at fine pitch (Mahajan et al., 2016), and logic dies are stacked face to face (Ingerly et al., 2019). Surveys of the field now list a wide range of fan-out, interposer and three-dimensional technologies (Lau, 2022).

Discussion of chiplets has concentrated on digital economics: yield of smaller dies, reuse of intellectual property, and mixing of process nodes (Iyer, 2016). The view taken here is that the change bears at least as heavily on analogue and mixed-signal design, and in a specific way. It relocates the interface. Circuits that used to sit at the edge of a chip and face the outside world now face another die a short distance away, and circuits that used to be buried in the middle of a system-on-chip find themselves at a die boundary. The argument is that this relocation changes the questions an analogue designer asks, and that the profession and its teaching should adjust.

Figure 1 sets out the levels at which a signal may now cross from one die to another or to the outside. Each level has its own geometry, parasitics and discharge environment, and a single product can use all of them. Five consequences follow for the circuits at the boundary.

The first objection is that standards make all this invisible. A designer who instantiates a standard die-to-die physical layer need know no more about it than about a memory compiler. That is true for the digital bus and is the point of standardisation. But someone designs the physical layer, and its transmitters, receivers, clock distribution and calibration loops are analogue circuits with new constraints. More to the point, the standards cover digital data. Supplies, references, clocks of high purity and analogue signal paths are outside them, and those are the crossings where analogue judgement is needed.

The second objection is economic. Analyses of chiplet cost show that the advantage depends on die size, volume and packaging cost, and that for many products a single die remains cheaper (Stow et al., 2017; Loh et al., 2021). Advanced packaging may therefore stay confined to large processors and accelerators, far from the consumer and industrial products where most analogue designers work. The objection has force for the present. It weakens to the extent that packaging capacity grows and that assemblies of mature-node dies on simpler substrates, which do not need the finest pitch, become ordinary.

The third objection concerns test, heat and mechanics. A die must be known to be good before it is committed to an expensive assembly, yet fine-pitch bumps are hard to probe and analogue performance is hard to guarantee from a wafer-level test; once assembled, internal interfaces are no longer reachable from outside (Marinissen and Zorian, 2009). A standard for test access in stacked dies exists (IEEE, 2020) but addresses digital access. Stacked and closely placed dies heat one another and are stressed mechanically by mismatched thermal expansion, which shifts the parameters of precision analogue circuits; such challenges have been recognised since the early work on three-dimensional integration (Knickerbocker et al., 2008). These are real obstacles. They are also, in large part, analogue and mixed-signal problems, and so they support the claim that the field is being drawn into packaging more than they refute it.

For practising designers the first implication is that the package model belongs in the schematic from the start. Bump maps, interposer routing and the power network of neighbouring dies determine the load, the coupling and the supply seen by an interface circuit, and treating them as a late extraction step repeats, at higher cost, the mistake of ignoring layout parasitics on chip. The second is that specifications must be written for the die as a component of an assembly: discharge levels for internal bumps, noise allowed on a shared reference, the thermal environment created by a neighbour. The Heterogeneous Integration Roadmap treats such co-design as a central need (IEEE EPS, 2019).

For tools the implication is that the boundaries between chip, package and board simulation have to become thinner. Analogue verification today assumes one process design kit and one extracted netlist. An assembly has several kits, an interposer or substrate technology with its own extraction, and electromagnetic, thermal and mechanical interactions between them. Flows that can hold all of this for a digital timing check are appearing. Flows that let an analogue designer simulate a signal path across three dies with trustworthy parasitics and a consistent treatment of supply and substrate are less mature.

For teaching the implication is modest in content and significant in emphasis. Students of analogue design learn the pad, the bond wire and the fifty-ohm line as the facts of life at the chip boundary. They should also meet the microbump, the through-silicon via and the lumped short link, learn how protection requirements depend on where an interface sits, and practise partitioning a mixed-signal system across dies as a design exercise with electrical consequences. None of this displaces device physics or feedback theory. It changes the examples.

There is an organisational implication as well. Package design has usually been the work of a separate team that receives a bump map late in the project. If the interposer carries analogue signals, references and supplies whose quality decides whether a converter meets its specification, the package engineer and the circuit designer need a shared model and an agreed budget from the first floorplan, much as layout and circuit design had to be brought together when parasitics began to dominate on chip.

Chiplets and advanced packaging are usually presented as a digital cost story. The position taken here is that they move the analogue designer's interface from the edge of the package to its interior, and that this alters the load, the protection, the supply and the choice of process in ways that reward deliberate design. The objections from standardisation, economics and test limit how fast and how widely the change will be felt, but each points back to analogue questions that someone must answer. Designers who learn to think of the package as part of the circuit will be better placed than those who wait for the interface to be defined for them.

To be declared by the author(s) before publication.

To be declared by the author(s) before publication.