The scaling rules set out by Dennard et al. (1974) gave the semiconductor industry a simple contract. If every dimension and the supply voltage were reduced by the same factor, transistors became faster, denser and no more power-hungry per unit area, and the doubling of component counts anticipated by Moore (1965) could continue. Designers took part mainly as recipients: each node arrived with a rule deck, and a layout drawn for the old node could be shrunk to fit the new one. Voltage scaling stalled first, then the patterning of ever finer pitches became difficult and expensive, and the contract lapsed (Kuhn, 2012; Bohr and Young, 2017).

What replaced it is a negotiated process. Before a node is defined, technologists and designers examine together which combinations of pitches, device structures and cell layouts give the best power, performance and area for representative circuits, and adjust both the process and the design rules in response. Liebmann et al. (2016) describe how this practice, design-technology co-optimisation or DTCO, grew out of the restrictions imposed by sub-resolution lithography. Yeric (2015) argued from the design side that with pitch scaling slowing, such co-optimisation would have to supply an increasing share of each node's benefit.

The introduction of gate-all-around (GAA) transistors, in which the gate surrounds horizontal sheets of silicon stacked one above another, gives the practice new material to work with. The nanosheet offers design freedoms that the fin did not, and it arrives together with changes in cell construction and power delivery that alter what the router sees. This review organises the published considerations by level: device, standard cell and routing.

This is a narrative review of the open literature: device and technology conference papers, journal articles, reference texts and the public roadmap. Foundry process details are confidential, and much of what is published comes from research consortia and from predictive design kits such as ASAP7 (Clark et al., 2016), so the account describes directions and trade-offs and does not attribute specific dimensions to any commercial node. Node names are treated as labels. The review does not cover memory-specific co-optimisation beyond a brief mention, nor two-dimensional channel materials, and it makes no claim to completeness.

A planar transistor loses control of its channel as the gate is shortened, because the drain field reaches under the gate. Wrapping the gate around more of the channel restores control, and the family of multiple-gate devices reviewed by Colinge (2004) follows from that principle; the underlying electrostatics are set out in standard texts (Taur and Ning, 2009). The FinFET of Hisamoto et al. (2000) placed the gate on both sides of a thin vertical fin, and the structure entered volume manufacture as the tri-gate transistor (Auth et al., 2012). Successive FinFET nodes made fins taller and thinner and reduced the number of fins per device.

That path ends when a device has one or two fins and the fin cannot be made usefully taller. The gate-all-around structure extends it. Silicon nanowire transistors with the gate on every side were demonstrated in research well before they were needed (Singh et al., 2006), and later work showed that vertically stacked wires could be built on bulk silicon in a replacement metal gate flow close to that of the FinFET (Mertens et al., 2016). Widening the wire into a sheet raises the drive current per footprint, and stacked nanosheets were presented as the successor to the fin by Loubet et al. (2017). A manufacturing technology built on such a multi-bridge-channel device followed (Bae et al., 2018).

The property of the nanosheet most often cited by designers is that its width is defined by lithography and can in principle take any value within a range. Fin devices are quantised: drive strength changes in whole fins, and a cell with two fins cannot be given a little more current. A sheet can be drawn wider for speed or narrower for low capacitance and leakage, which allows a library to offer high-performance and high-density variants on the same process (Loubet et al., 2017). The freedom is bounded. Wide sheets are harder to release and to fill uniformly with gate metal, and electrostatic control weakens somewhat as the sheet widens, so each process supports only a set of permitted widths.

The number of sheets in the stack is fixed by the process and not by the designer, yet it shapes every cell. More sheets give more current in the same footprint and also more gate and fringe capacitance, taller source and drain regions and a more demanding etch, so the gain per added sheet diminishes. Between the sheets, inner spacers separate the gate from the source and drain; their thickness trades parasitic capacitance against the resistance of the path into the channel. The space between sheets also limits the thickness of the work-function metals that set the threshold voltage, which makes it harder to offer the several threshold options that low-power design relies on. Self-heating is a further concern, since the sheets are surrounded by materials that conduct heat poorly.

For co-optimisation, the lesson is that device choices are not judged by transistor figures of merit alone. Whether an extra sheet or a thinner spacer is worthwhile depends on the load the device drives, and in a dense logic block that load is increasingly the wiring. The evaluation therefore has to be made on circuits, typically ring oscillators with representative wire loads and then placed and routed blocks.

Static memory deserves a brief mention, because its bit cell is the densest layout on any chip and is co-optimised separately from logic. The cell needs a particular ratio of strengths among its pull-down, pass-gate and pull-up transistors, which fin quantisation made awkward to achieve. Adjustable sheet width restores some of that freedom, and the bit cell is consequently one of the first circuits on which a nanosheet process is assessed.

The height of a standard cell is measured in tracks, the number of minimum-pitch horizontal metal lines that fit across it. Reducing the track count has been the main source of area scaling in recent nodes, and each reduction removes something: fins, routing tracks inside the cell, or room for the power rails. With nanosheets the devices can be kept reasonably wide while the cell shrinks, and what limits the height becomes the space between the n-type and p-type devices and the width taken by the rails. Table 1 lists the main scaling measures at each level with their benefits and costs, and Figure 1 shows how the levels depend on one another.

The separation between n and p devices is set by patterning margins for the work-function metals and the gate cut. The forksheet device addresses it directly: a dielectric wall is placed between the n and p sheet stacks, so that they can sit much closer, at the price of a gate that wraps three sides of each sheet and not four. Weckx et al. (2017) examined the structure for static memory cells as an instance of device and design being optimised together. The complementary FET goes further and stacks the n-type device on top of the p-type device, or the reverse, removing the lateral separation altogether (Ryckaert et al., 2018). Its cell can be very low, but the connections to the lower device and the choice of which signals leave the cell at which level become the central layout problem.

Power rails are the other consumer of cell height. In a conventional cell they run in the lowest metal layers along the top and bottom edges and must be wide to carry current. Moving them out of the signal stack frees tracks. A buried power rail is a metal line placed below the devices, in the isolation between them; with a backside power delivery network, the rails are fed through the thinned wafer from a dedicated grid on its rear face. Prasad et al. (2019) analysed both options on a processor design and showed that the benefit appears as reduced supply voltage drop and relieved routing congestion as well as cell area. The costs lie in wafer bonding and thinning, in alignment between the two faces, and in removing heat from devices that no longer sit on a thick silicon substrate.

Smaller measures add up alongside these. Placing the gate contact over the active region, replacing the dummy gates between cells with a single diffusion break, and self-aligning gate cuts and contacts each recover a fraction of a track or a gate pitch. Each also tightens the coupling between layout and process, because the layout patterns permitted are those the process module was tuned to print.

A cell that is small but cannot be reached is of no use. As track counts fall, the pins of a cell have fewer points at which a wire from the routing layers can land, and neighbouring cells compete for the same tracks. Pin accessibility has therefore become a criterion in cell design, checked by placing and routing trial blocks during technology definition and not after it. The algorithms involved are those of conventional physical design (Kahng et al., 2011); what has changed is that their outcome feeds back into the cell architecture and even into the choice of metal pitches.

Patterning shapes the routing fabric. The lower metal layers of advanced nodes are drawn as unidirectional lines on a fixed grid, with line ends defined by separate cut patterns, because that is what multiple patterning and extreme ultraviolet exposure can print with adequate margin; the optical reasons are covered in lithography texts (Mack, 2007). The designer loses the freedom to jog a wire within a layer, and every change of direction costs a via. Rules on cut spacing and on the minimum length of a line segment decide whether two pins in adjacent cells can both be connected, so they belong to the co-optimisation as much as the cell layout does.

Resistance is the third issue. When the width of a copper line approaches the mean free path of its electrons, scattering at surfaces and grain boundaries raises the resistivity, and the barrier and liner layers take a growing share of the cross-section. Gall (2016) showed that the product of bulk resistivity and mean free path predicts which metals suffer least from this size effect, which is the basis for the interest in cobalt, ruthenium and molybdenum for the narrowest lines and vias. For the circuit, high wire and via resistance means that the delay of a short net may be dominated by the wire and not by the transistor that drives it. This weakens the return on device improvements and strengthens the case for evaluating every technology option on routed designs.

The three levels cannot be closed one at a time. A wider sheet raises drive current but may force a taller cell; a lower cell saves area but reduces pin access, and the router then needs more length and more vias, which adds resistance that the wider sheet was meant to overcome. Moving power to the backside relaxes the cell and the lower metal layers at once and so changes the best choice of track height and metal pitch. The published studies handle these loops by building a provisional process design kit and cell library for each candidate, running a small set of benchmark designs through synthesis, placement and routing, and comparing the outcomes.

The scope of the exercise is also widening. The roadmap now treats system-technology co-optimisation, which adds three-dimensional stacking, packaging and the partitioning of a product across several dice, as the continuation of DTCO (IEEE, 2022). Salahuddin et al. (2018) make a related argument: that future gains will come from combining device, memory and architectural changes and not from any one of them. On that view, the nanosheet transistor is one move in a longer game whose pieces are increasingly above the device.

Several matters are not resolved in the open literature. Public evidence on variability in nanosheet devices, in particular variation of sheet thickness and its effect on threshold voltage across a library of different widths, is thin compared with what was published for fins. The thermal behaviour of blocks with backside power delivery has been modelled more than it has been measured. Predictive design kits, on which academic work depends, lag the industry: the most widely used one models a fin process, and openly available kits for nanosheets with backside power are only beginning to appear. As a result, published place-and-route studies of such technologies are difficult to reproduce.

There is also a methodological gap. Co-optimisation studies report results for a handful of benchmark blocks, and how far the conclusions carry over to designs with different mixes of logic, memory and wiring is seldom tested. Automating the loop, so that cell libraries are generated and assessed for many candidate rule sets without manual layout, is an active area and a natural meeting point for process engineers and the design automation community.

Gate-all-around transistors do not restore the old pattern in which a better device translated directly into a better chip. Their value is realised through the standard cell, the power delivery network and the routing fabric, and each of those constrains the device in return. The literature reviewed here points consistently to the same working method: candidate technologies are judged on placed and routed circuits, with wire resistance and pin access counted from the start. The questions that remain open, on variability, heat and the generality of benchmark results, are ones on which openly published data would be particularly valuable.

To be declared by the author(s) before publication.

To be declared by the author(s) before publication.