CONCURRENT ERROR DETECTABLE CARRY SELECT ADDER WITH EASY TESTABILITY OF 16-BITS

Abstract

As the process shrink of integrated circuits 
advances and the integration density 
increases, reliability of integrated circuits in 
field becomes an issue. For critical systems 
such as server class computers and 
embedded systems, concurrent detection of 
errors is important. Addition is the most 
basic arithmetic operation, and a lot of 
adders are used in VLSIs. Reliable adders 
are important for realizing reliable systems. 
In these previously proposed concurrent 
error detectable adders, any erroneous 
output caused by a single fault can be 
detected. However, an erroneous output 
caused by multiple faults is not guaranteed 
to be detected. If a second fault has occurred 
before the first fault is found through 
detection of an erroneous output, the 
concurrent error detectability can be lost. 
For reliable adders, it is crucial that the first 
fault is noticed before a second fault occurs. 
Effective self-repairing can be achieved if 
the fault along with its exact location can be 
determined. In this work, a self repairing 
hybrid adder is proposed with fault 
localization. It uses the advantages of ripple 
carry adder and carry-select adder to reduce 
the delay and area overhead.